(1) Field of the Invention
This invention relates to a power semiconductor device and a fabrication method thereof, and more particularly relates to a fabrication of a power semiconductor device by using fewer masks to reduce cost.
(2) Description of the Prior Art
Price competition has become an important issue in semiconductor industry. In order to enhance product's competition, it is an effective way to reduce the number of masks applied in the fabrication process.
Generally, the fabrication process of a trenched power semiconductor device needs five masks for defining the location of gate trenches, body regions and termination regions, source doped regions, source contact window, and metal pattern. In present, some self-aligned technologies have been developed for reducing the number of masks. However, most of these self-aligned technologies are applied for defining the source doped regions and the source contact windows for reducing the number of masks. Seldom of the solutions can be applied to the lithographic steps for defining the other structures.